XC7Z020-2CLG484I

XC7Z020-2CLG484I is an AMD/Xilinx Zynq-7000 SoC combining a dual-core Arm Cortex-A9 processing system with Artix-7-class programmable logic. The XC7Z020 has 85,000 logic cells, 53,200 LUTs, 106,400 flip-flops, 220 DSP slices and 4.9 Mb of programmable-logic block RAM. These are Xilinx resources, not Intel/Altera adaptive logic modules (ALMs).

How should the ordering code be checked? -2 is the speed grade, CLG484 identifies the 484-ball package, and I is the industrial junction-temperature range of -40°C to +100°C. The CLG484 package measures 19 × 19 mm with 0.8 mm ball pitch. It exposes up to 200 programmable-logic SelectIO pins; processor-system I/O is a separate resource, not another name for those 200 pins.

Does 766 MHz describe the FPGA fabric? No. DS190 lists up to 766 MHz for the -2 Z-7020 processor system. Programmable-logic timing depends on the implemented design and timing constraints. Similarly, the 256 KB processor on-chip memory, 512 KB L2 cache and 4.9 Mb PL block RAM are separate resources and should not be combined into one RAM specification.

Before ordering or substituting, match the complete -2CLG484I code against the approved BOM, board footprint, power design and timing closure. Request full top-marking and label photos, lot/date-code details, package and ball-condition evidence, moisture-handling history and available traceability records. Do not infer original packing, absence of reballing or application qualification from the part number alone.

Technical reference checked October 24, 2026: AMD/Xilinx Zynq-7000 SoC Data Sheet: Overview, DS190 v1.11.1, July 2, 2018; Tables 1, 2 and 7. The linked overview describes device resources; consult the applicable DC/switching datasheet and design tools for electrical sign-off.