MR2A16AVYS35

MR2A16AVYS35 is an Everspin Technologies magnetoresistive random-access memory (MRAM). Its density is 4 Mbit, organized as 256K words of 16 bits. It offers a parallel asynchronous interface with SRAM-compatible 35 ns read/write timing and nonvolatile data storage. It should not be described as a 16 Mbit SRAM.

What does the full ordering code specify? In Everspin's MR2A16A ordering table, V identifies the extended -40 to +105 C operating range, YS identifies the 44-pin TSOP Type II package, and 35 identifies the 35 ns speed. MR2A16AVYS35 is the tray ordering code; the separate R-suffixed code denotes tape-and-reel shipping. Confirm the actual offered packaging and condition in the quotation.

Can this replace a conventional SRAM or another MRAM? SRAM-compatible timing does not approve a drop-in replacement. The responsible engineer should compare pin assignments, supply limits, read/write control, power sequencing, retention requirements and the application's operating conditions. AEC-Q100 or military screening should not be inferred from this extended-temperature code.

For an RFQ, specify MR2A16AVYS35, required quantity and delivery target. Ask for full-marking and packaging photos, date-code and lot information, available traceability, and the inspection or testing included in the offer. Listed quantity is not a reservation of a specific lot.

Technical references checked October 24, 2026: Everspin MR2A16A datasheet Rev. 11.3 (March 2018), pages 1, 15 and 16, and Everspin's May 2012 magnetic-immunity product note, which names MR2A16AVYS35 explicitly.